NXP Debuts i.MX 95 Armed with 3D Graphics and NPU Enhancements

We proceed our protection of CES this week, this time with today’s reveal by NXP Semiconductors of the i.MX 95 household, a brand new addition to the corporate’s i.MX 9 sequence of functions processors. The gadgets mix a number of high-performance compute parts, together with superior 3D graphics, neural processing, embedded safety, and extra.

The machine expands NXP’s i.MX 9 sequence, which incorporates the i.MX 93 announced again in November. Prior says that the corporate doesn’t see the 9 sequence as essentially changing NXP’s earlier i.MX 8 processor sequence, however extra as interleaving and augmenting the 8 sequence to be able to present a broad portfolio providing to the market.

A part of NXP’s i.MX 9 sequence of functions processors, i.MX 95 provides new NXP-developed NPU and ISP cores to the combo. Picture used courtesy of NXP

On this article, we study the options and specs of the brand new i.MX 95 functions processor and share evaluation from our interview with James Prior, product supervisor for NXP’s Superior Edge Processor Innovation Group.

An Structure Designed for Flexibility

In keeping with Prior, the important thing facet of the i.MX 95 structure is its flexibility. The processor’s fundamental CPU area consists of as much as six Arm Cortex A55 CPU cores organized in a coherent cluster. However there’s additionally a separate area with a real-time Arm Cortex M7 MCU. As well as, there’s a low-power real-time area powered by a low energy (security) Arm Cortex M33 CPU.

“All that is all put collectively in what we name our ‘Flex Domains’,” says Prior. “So engineers can combine collectively which items of IP they need to use in a selected area.” In different phrases, the principle CPU area can use the entire chip’s features and options (see picture beneath). But additionally the actual time MCU may be linked to totally different on-chip parts as properly. “They’re very versatile, not solely from us on a product definition aspect, however from the shopper aspect for his or her implementation,” says Prior.

The i.MX 95 block diagram. Flex Domains allow builders to have totally different compute elments use a wide range of peripherals and features. Picture used courtesy of NXP (Click on picture to enlarge)

Wealthy Multimedia Assets on Chip

In the meantime, there’s loads occurring within the i.MX 94’s ML (machine studying) and Multimedia block. This area consists of an Arm Mali 3D GPU core, but additionally an impartial 2D GPU with an actual time mix engine.

“This implies we are able to overlay the graphics from the 2D GPU on something that is in a part of the imaginative and prescient processing pipeline, whether or not that is an exterior community machine, a instantly linked digicam, or output from the 3D GPU,” says Prior, “All of that may be blended and offered.”

Prior says that the i.MX 95 is NXP’s first functions processor to assist LPDDR5 DRAM, enabling elevated bandwidth and future-proofing. However the machine additionally maintains compatibility with older LPDDR4X DRAM as a result of not everyone seems to be utilizing LPDDR5 but. The i.MX 95 additionally helps reminiscence encryption and in-line reminiscence correction.

The i.MX 95 additionally integrates a brand new picture sign processor (ISP) developed by NXP. In keeping with Prior, the  ISP is optimized for machine imaginative and prescient functions and helps two Areas of Curiosity. The ISP also can do HDR mixture of two exposures and superior de-noising and edge enhancement with assist for colour, monochrome and RGB-IR digicam sensors.

NPU Core Scheme Permits Scalability

One other key ingredient within the i.MX 95 processor structure is the machine’s embedded NPU. The i.MX 95 household is the primary i.MX functions processor household to combine the NXP-designed eIQ Neutron neural processing NPU (neural processing unit). NPUs usually are not new to NXPs’ chip designs. NXP’s lately launched microcontroller, the MCX-N, embeds an NPU.

We requested Prior what the NPU on the i.MX 95 has in widespread with the NPU on that microcontroller. “It is the identical however totally different,” he says.”It is the identical core IP and design, however one of many i.MX 95 is the excessive finish instantiation.” However whereas the efficiency ranges are totally different, they share a standard primary structure with assist for all the identical main neural community buildings (CNN, MLP, RNN, LSTM, TCN, and extra). That lets engineers use NXP’s eIQ software program improvement setting on each gadgets.

The i.MX 95 processor’s embedded NPU makes use of the identical primary {hardware} structure because the NPUs in decrease finish NXP gadgets, permitting customers to scale up as wanted. Picture used courtesy of NXP

“We bought numerous suggestions from the market,” says Prior, “Engineers who’re adopting AI/ML need scalability and so they need consistency. And we have been dealing with that with our eIQ ML software program improvement library. Bringing in a standard {hardware} platform beneath will increase scalability and reduces the quantity of redevelopment that must be achieved.” The NPU {hardware} scales from efficiency environment friendly 32 Ops/cycle to 2k Ops/cycle and past.

Lengthy Life Assist

To serve the wants of embedded functions, the NXP says that each one i.MX 8 sequence and that i.MX 9 sequence merchandise are assured for at least 15 years of availability as a result of they’re a part of the NXP product longevity program. Extra details about the iMX 95 is accessible within the i.MX 95 fact sheet. The corporate says the i.MX 95 functions processors are anticipated to start sampling for lead clients in 2H 2023.